1. Field of the Invention
The present invention relates to spatial light modulator (SLM) projection displays and more specifically to an improved clocking method for improved display performance.
2. Description of the Related Art
To achieve a satisfactory degree of intensity resolution in a display system using pulse width modulation (PWM), some display time periods (bit times) can be shorter than the time required to reload the pixels of the SLM. For some SLMs, for example a digital micromirror device(trademark) (DMD(trademark)), a technique for displaying such short bit times, called reset/release, causes the DMD mirrors to be released (to float in a flat state). Typically the DMD mirrors operate with dark field projection optics in a binary ON/OFF manner, for example mirrors tilted +10xc2x0 (binary 1 memory state under the mirrors) are ON and reflect light into the aperture of a projection lens while mirrors tilted xe2x88x9210xc2x0 (binary 0 memory state under the mirrors) reflect light into a xe2x80x98dark trapxe2x80x99 away from the projection lens. As a result, flat 0xc2x0 mirrors are in an ambiguous state, which can allow stray light to enter the aperture, so as to degrade the contrast and exhibit undesirable memory effects. In addition, when used in a system incorporating the socalled block-reset technique, two additional artifacts can occur; i.e., (1) horizontal lines at the reset block boundaries, and (2) a xe2x80x9cvenetian blindxe2x80x9d effect across the reset blocks.
FIG. 1 is a binary PWM sequence pattern for a SLM. The first diagram 10 shows one frame refresh period for a 5-bit binary system (5-bits are used for simplification, typical systems use 8-bits or more) with bits ranging from the least significant bit (LSB) 100 to the most significant bit (MSB) 104. Bit 0100, the LSB, accounts for 1/(2n-1) of the refresh period, where n is the number of bits. Then each succeeding bit represents double the time of its preceding bit; e.g., bit 1101 represents 2xc3x97 LSB, bit 2102 represents 4xc3x97 LSB, bit 3103 represents 8xc3x97 LSB, bit 4104 represents 16xc3x97 LSB, of the total refresh time. In a DMD, the memory cell under the mirror is addressed in a binary fashion according to this PWM sequence. The mirrors tilt xc2x1X degrees depending on the binary state of its memory cell; e.g.; a mirror might tilt +10xc2x0 if its associated memory cell has a binary 1 state and xe2x88x9210xc2x0 if its memory cell has a binary 0 state. The second diagram 11 is an example of a memory cell, whose PWM sequence is binary 01111. When bit 0, 1, 2, or 3 is loaded, the memory cell is a binary state 1 and when reset to this state the mirror is ON and reflects light into the lens aperture. When bit 4 is loaded, the memory cell is a binary state 0 and when reset to this state the mirror is OFF and reflects light away from the lens aperture into a xe2x80x98dark trapxe2x80x99. In this case, the mirror reflects light for {fraction (15/31)} or 48% of the refresh period and is dark for {fraction (16/31)} or 52% of the refresh period, since the MSB is a binary 0.
The human visual system effectively integrates the pulsed light from the mirror to form the perception of a level of light intensity. The gray scale level is proportional to the percentage of time the mirror is ON during the refresh time. The 48% level of the above example represents a gray level near the middle of the scale from black to white intensity. Similarly, the third diagram 12 is an example of a memory cell, whose PWM sequence is binary 11010. When bit 1, 3 or 4 is loaded, the memory cell is a binary state 1 and when reset to this state the mirror is ON and reflects light into the lens aperture. When bit 0 or 2 is loaded, the memory cell is a binary state 0 and when reset to this state the mirror is-OFF and reflects light away from the lens aperture into a xe2x80x98dark trapxe2x80x99. In this case, the mirror reflects light for {fraction (26/31)} or 84% of the refresh period and is dark for {fraction (5/31)} or 16% of the refresh period.
In a PWM SLM (example DMD), the device is loaded with the MSB and left for approximately xc2xd the refresh time, then loaded with the second MSB and left for xc2xc the refresh time, then loaded with the third MSB and left for xe2x85x9 the refresh time, and so on until the LSB is loaded and left for 1/(2n-1) of the refresh time. However, it is not necessary to load and reset a bit and leave it for the full duration of time. Instead, the longer MSB periods can be broken into smaller segment, which are distributed throughout the refresh time and the mirror is addressed multiple times so as to add up to the total bit period duration. This technique, called xe2x80x9cbitsplitting,xe2x80x9d is illustrated in FIG. 2 and can create a more pleasing image over that of leaving the mirror in one position for the whole bit period. The first diagram 20 shows the PWM-example of FIG. 1 using xe2x80x9cbit-splittingxe2x80x9d. If the SLM is a DMD, the memory cells can be loaded without affecting the state of the mirrors since the mirror superstructure has an inherent mechanical latch that allows the mirrors, once reset, to remain in that state independent of the memory cell state until the mirrors are once again reset. As a result, the cells can be loaded without upsetting the previous mirror state. It is desirable to continuously load the memory and reset the mirrors after equal intervals of time. In the diagram 20 bit 1 is loaded once during the refresh period and left for a period of time. Bit 2 is loaded twice during the refresh period and left each time for the same time as bit 1. Similarly, bits 3 and 4 are loaded 4 and eight times, respectively, during the refresh period and each time left for the same period of time as bit 1. However, notice in the diagram that bit 0 is loaded and left in its state for a period of time equal to only xc2xd that of bit 1. The reason for this is that bit 0 has only xc2xd the weight of bit 1. In this example, there is not enough time to load the memory array during bit 0. Herein lies the problem to be address by this invention. But first, the second diagram 21 shows the xe2x80x9cbitsplittingxe2x80x9d example for the 48% intensity level discussed in FIG. 1. Here bit 1 is a binary 1 for one split-bit (sb) period, bit 2 is a binary 1 for two separate sb periods, bit 3 is a binary 1 for four separate sb periods, and bit 4 is a binary 0 for eight sb periods, but bit 0 is a binary 1 for only xc2xd split-bit period. Similarly, the third diagram 22 shows the xe2x80x9cbit-splittingxe2x80x9d example for the 84% intensity level discussed in FIG. 1. Here bit 0 is a binary 0 for xc2xd a split-bit period, bit 1 is a binary 1 for one split-bit (sb) period, bit 2 is a binary 0 for two separate sb periods, bit 3 is a binary 1 for four separate sb periods, and bit 4 is a binary 1 for eight sb periods.
SLMS, and DMDs in particular, have typically been addressed globally; i.e., all cells are addressed and then reset simultaneously, as illustrated in FIG. 3. While data is being loaded into the DMD, the mirrors remain in their previous state due to a bias voltage, which is applied to the mirror superstructure. That is, after the device is loaded with the new data bit plane, the bias voltage is reset, allowing the mirrors to assume their respective state corresponding to this new bit plane. FIG. 3 shows the memory being loaded, the reset pulse, the corresponding multiple split-bits being displayed, and the PWM sequence for the bits. For example, in operation, while bit 3 is displayed 30, bit 4 is being loaded into memory 31. Once bit 4 is loaded, the reset pulse 32 is applied causing the mirrors to go to the new bit 4 state 33. Then while bit 4 is displayed 33, bit 2 is loaded into memory 34 and the reset pulse 35 is applied causing the mirrors to go to the next bit state 236, and so on throughout the PWM sequence 37.
As mentioned earlier, a fundamental limitation of this load-reset method occurs when a split-bit (bit 0) requires a shorter display duration than the time needed to load the entire device""s memory cells. In the past, this problem has been overcome by using a clear operation rather than a reset operation for bit 0, since in a DMD a global clear can be performed in a small fraction of the time required to load the entire device. FIG. 4 illustrates this technique for generating the required xc2xd split-bit period for bit 0, which again shows the memory being loaded, the reset pulse, the corresponding displayed bits, and the PWM sequence 400. The operation is the same except for bit 0. For example, bit 4 is loaded into memory 40, while bit 3 is displayed 41, and then the reset pulse 42 is used to reset the mirrors to their bit 4 state 43. Bit 0 is then loaded into memory 44 in a normal manner and the reset pulse 45 is applied to reset the mirrors to the bit 0 state 46. However, a global clear 47, where all bits are set to 0 state, is executed and part way through the bit 0 split-bit period reset pulse 48 is applied, which quickly turns all mirrors OFF 49, where they remain for one split-bit period while the next normal bit 1 is loaded into memory 401. This technique provides the desired xe2x80x9cshortxe2x80x9d bit, but it requires that all the mirrors remain OFF for one split-bit period 49, which significantly decreases the system brightness. In addition, if the system speed requires that the bit 0 time becomes too short to allow for a global clear of the device, this technique will not work.
More recently, a new DMD architecture called phased-reset has been used to overcome the problems discussed above for generating the xe2x80x9cshort bitxe2x80x9d in a global reset device. FIG. 5 shows a portion of the PWM sequence 50 for phased-reset operation of a DMD. In this approach, the DMD is partitioned into blocks; e.g., a 640xc3x97480 VGA DMD may be divided into 12 horizontal blocks of 640xc3x9740 pixels (mirrors) each. In the example of FIG. 5, the device is divided into eight blocks. Two distinctions are made for these phased-reset devices over global devices, as follows:
(1) each block can be loaded and reset independently from the other blocks, and
(2) load and reset functions within a given block are no longer tied together, but may be separated by a period of time. (For global operation, a reset immediately follows a load)
In phased-reset operation, each reset block is independently loaded and reset. In this case, bit 4 is loaded and reset 52, on a phased block basis, while bit 3 is being displayed 51. Since the display period of bit 0 is too short to allow the entire device to be loaded, the bit 0 data is loaded, but the mirrors are not immediately reset, early in the bit 4 display period. At the appropriate time, a block of mirrors is reset 55, allowing them to be displayed 53 in the appropriate bit 0 state. Then bit 1 is loaded and an immediate reset 56 is applied in a normal manner, allowing the mirror to go to the bit state. The process then continues with the loading and reset of the next block of mirrors. After all of the bit 0 display periods are complete and the bit 1 periods started, the process continues with bit 4. In this method, bit 0 need not fully accommodate a device load because the phased structure allows for the display time of the next normal bit to begin immediately as the different blocks are loaded. This method overcomes the need to turn the mirrors OFF while loading the next normal bit, which causes degradation in the system brightness, as discussed earlier, but it does extend the MSB time somewhat. However, this method works as long as the block loading time plus the mirror settling time is less than the bit 0 time.
In modern systems where the bit times are continuously becoming shorter and shorter, it is possible for the bit 0 time to be shorter than the block loading time plus mirror settling time of bit 0. FIG. 6a is a diagram showing another approach, called reset-release timing, used in a phased system where the block loading time plus the mirror settling time is longer than the bit 0 time. The difference here from the phased reset method discussed above is that at the end of the reset-release period the mirrors are released to a flat state and held while the next bit is loaded. This is accomplished by turning the mirror bias OFF and allowing them to float around the 0xc2x0 position. This shows the data to be loaded into memory, the reset timing, and the reflected light response from the mirrors. While the mirrors are in their selected state from normal bit A 600, the reset-release (rr) bit is loaded 601 into memory, but the mirrors are not reset immediately. At the appropriate time (after delay), a reset pulse 602 occurs setting the mirrors 603 according to the rr data in memory. Then at the end of the short bit 0 period, the mirrors are released 604 by turning OFF the mirror bias 605. In the absence of a bias, the mirrors go to a flat state 606 and remain there while data for the next normal bit B 607 is loaded into memory. The bias is then turned back ON 608 and the mirrors assume their bit B positions 609. The graph to the right of the diagram is a plot of the reset timing pulse 610 and the optical response 611 from the mirrors. The rr artifacts 612 are also shown with some stray light getting into the lens aperture causing undesirable artifacts.
FIG. 6b illustrates the timing for the reset-release method of FIG. 6a. This diagram shows a normal bit A being loaded 60 and reset 61, then the reset-release (rr) bit is loaded 62 but not immediately reset in the normal fashion. Then at the appropriate time the rr bit is reset 63, allowing the mirrors to go to their appropriate state, and released 64 at the end of the bit 0 time period, when the mirror bias is turned OFF. Once released, the mirrors go to and remain in a flat (approximately 0xc2x0) position while the next bit B is loaded 65. Once loaded, the mirror bias is turned back ON 66 allowing the mirrors to go to their new state (+10xc2x0 or xe2x88x9210xc2x0) at which point the normal sequence of loading 67 and resetting 68 the next bit continues. The problem with the reset-release method is that the flat mirrors lead to additional optical artifacts, such as stray light entering the aperture causing horizontal lines at the reset block boundaries, a xe2x80x9cvenetian blindxe2x80x9d effect across the reset blocks, and lower system contrast due to higher dark levels.
What is needed is a method to turn the mirrors OFF while loading the next bit after the short bit in order to avoid the undesirable artifacts of the method(s) discussed above. However, this is not a trivial matter for such short bit times and is complicated by the fact that the combination of data and reset operations are performed independently on each block in a phased manner. In addition, matters are further complicated by the additional restrictions that a block clear cannot be performed on one block while loading another block. However, the method of this invention addresses these needs and provides a high performance solution, albeit with some limitations as to DMD type and bit ordering.
This invention discloses a DMD PWM clocking method, called xe2x80x9cjog clearxe2x80x9d, for generating short bit periods where block data clears are inserted between block data loads within a frame refresh period. The method significantly reduces the minimum short bit duration without requiring reset-release methods.
Short bit times are needed for the LSB(s) in PWM devices, such as the DMD, where the memory load and mirror settling times are greater than the split-bit display time. Currently, techniques such as reset-release are used to generate these short bit periods, but this requires that the mirrors be released to the flat state while data for the next normal bit is loaded into memory. Having the mirrors flat even for a short period of time reduces the contrast and brightness of the system and introduces artifacts in the form of horizontal lines at the block boundaries and generates a xe2x80x9cvenetian blindxe2x80x9d effect across blocks.
The jog-clear method of this invention causes the mirrors to turn OFF while data for the next bit is loaded, thereby eliminating these undesirable artifacts. However, quickly turning the mirrors OFF to a dark state is a non-trivial matter since the combination of data and reset operations have to be performed independently on each group in a phased manner and is further complicated by the fact that one block cannot be cleared while another block is being loaded. This introduces a skew in the short bit timing, which must be removed elsewhere within the frame refresh period.
The jog-clear method of this invention requires that the DMD/controller be capable of quickly clearing a reset block between loads of two other reset blocks. Such devices are now available, for example a 0.7-inch diagonal XGA DMD, as well as others. The method also introduces bit-ordering limitations to deal with removing the skew from each frame refresh period.
Major advantages of this new method include:
the elimination of visible lines at block boundaries,
the elimination of the xe2x80x9cvenetian blindxe2x80x9d effect, and
significantly reduced black level.